A low-cost and highly compact FPGA-based encryption/decryption architecture for AES algorithm



FPGA, AES, Advanced Encryption Standard algorithm,, encryptor / decryptor, GF (2^8) multiplier


Nowadays, the design of ultra-compact area advanced encryption standard (AES) architectures is highly demanded by the electronics industry since many of these architectures are embedded in portable devices, such as smart phones, tablets, etc., in which the area is critically limited. Until now, many approaches have been proposed to create high-processing and compact architectures. However, the area consumption is still a factor to be improved. In this paper, a highly compact encryption/decryption architecture, which is implemented in a low-cost FPGA, to efficiently simulate the AES algorithm, is proposed. Specifically, an optimized Galois Field Multiplier, which is the most demanding operation in terms of area consumption and processing speed, involved in Mix-Columns and Inverse Mix-Columns transformations, is presented. Therefore, the optimization of the proposed GF (2^8) multiplier by two has allowed to us create an ultra-compact Mix-Columns circuit since this circuit involves large number of multiplications. In addition, the design involves a routing circuit which allowed the proposed architecture to perform encryption or decryption by using common modules. The results demonstrate that the proposed digital circuit expends fewer LUTs and fewer registers when compared with the most compact encryption/decryption architectures reported to date.


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Author Biographies

Christian Equihua, Instituto Politécnico Nacional

Christian Equihua received the BS degree in Electronics and Telecommunications at "Universidad Politecnica de Texcoco (UPTEX)" in December 2006, currently he is studying the M.Sc. in Microelectronics at ESIME campus Culhuacan from the "Instituto Politecnico Nacional" in Mexico City, Mexico. His current interest is oriented towards information security, specifically crypto-hardware.

Esteban Anides, Instituto Politécnico Nacional

Esteban Anides received the BS degree at Universidad Politecnica de Texcoco, Mexico, in 2018. Currently, he is a Master student at the Instituto Politecnico Nacional, Mexico. His research interest are: signal processing, neural networks, adaptive systems, digital filtering, and digital design.

Jorge Luis García, Instituto Politécnico Nacional

Jorge Luis García received the BS degree at Instituto Politécnico Nacional, Mexico, in 2018. Currently, he is a Master student at the Instituto Politecnico Nacional, Mexico. His research interest is linked to robotics and neuromorphic circuits.

Eduardo Vázquez, Instituto Politécnico Nacional

Eduardo Vázquez studied a Bachelor of Computer Science at UAM - Iztapalapa. He obtained his master's and PhD degrees at the Center for Research and Advanced Studies of the National Polytechnic Institute (CINVESTAV, Zacatenco Unit) in 2002 and 2012, respectively. He is currently professor at the Higher School of Mechanical and Electrical Engineering, Culhuacan Unit.

Gabriel Sánchez, Instituto Politécnico Nacional

Gabriel Sánchez received the BS degree in Computer Science Engineering and the PhD degree in Electronic and Communications in 1999 and 2005, respectively, from the National Polytechnic Institute, Mexico City. He is a member of the National Researchers System of Mexico. His principal research interest is related to artificial neural networks.

Juan-Gerardo Avalos, Instituto Politécnico Nacional

Juan Gerardo Avalos was born in Mexico in 1984. He received the M.Sc. in microelectronics from the National Polytechnic Institute, Mexico, in 2010 and the Ph.D. degree in electronics and communications engineering from the National Polytechnic Institute, Mexico, in 2014. From 2011 to 2012 he was visiting researcher at the Vienna University of Technology, Austria. He is currently working as a Professor in the department of computer engineering, at the National Polytechnic Institute, Mexico.

Giovanny Sánchez, Instituto Politecnico Nacional

Giovanny Sánchez received the M.S. degree at Instituto Politecnico Nacional, Mexico, in 2008, and the Ph.D. degree at Universitat Politecnica de Catalunya, Spain, in 2014. His research is focused on developing early auditory neural processing systems, neural-based cryptosystems in neuromorphic hardware, image and audio processing. Currently, he is an Associate Professor in the Instituto Politecnico Nacional, Mexico.


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How to Cite

Equihua, C., Anides, E., García, J. L., Vázquez, E., Sánchez, G., Avalos, J.-G., & Sánchez, G. (2021). A low-cost and highly compact FPGA-based encryption/decryption architecture for AES algorithm . IEEE Latin America Transactions, 19(9), 1443–1450. Retrieved from https://latamt.ieeer9.org/index.php/transactions/article/view/4611