A Scalable Configurable Neuromorphic Architecture to Efficiently Compute Spatial Image Filtering of High Image Resolution and Size

Abstract

The processing of spatial image filters has been commonly used in many advanced digital image processing algorithms applied in applications such as pattern recognition and behavior recognition. Currently, some authors intend to implement these filters in parallel hardware architectures to process images of very high resolution (large structured arrays of data). However, these implementations require a large number of arithmetic circuits that are area and power intensive. During the last ten years, several computer scientists have made intense efforts in developing novel neural arithmetic circuits such as adders, subtracters, divisors and multipliers that are based on Spiking Neural P systems (SN P systems). These efforts aim at improving the performance of the conventional binary circuits by taking advantage of the intrinsic parallelism of SN P systems. Nevertheless, many of these approaches still require parallel hardware architectures (neuromorphic systems) to validate their performance in terms of area and processing speed. In this article we propose a multi-FPGA system to support an array of very large-scale SN P neurons to process high image resolution at high processing speeds. These neurons can be simulated by using a scalable configurable parallel hardware architecture, where its basic processing unit is a single SN P neuron. Here, this neuron performs addition, subtraction, multiplication and division, to perform image filtering such as Averaging and Laplacian Gaussian. This has been demonstrated using Kintex-7 Field- Programmable Gate Array (FPGA) development kits. Our results show that the proposed architecture achieves significantly higher processing speeds compared to the existing Graphical Processing Units (GPU), advanced CPUs and FPGA-based solutions.