FrodoKEM Hardware Implementation for Post-Quantum Cryptography

Authors

Keywords:

Lattice-based cryptography, High-Level Synthesis (HLS), FPGA, Post-Quantum Cryptography, FrodoKEM, Hardware implementation

Abstract

FrodoKEM, a key encapsulation mechanism (KEM) based on the learning with errors (LWE) problem, would be included for standardization by the International Organization for Standardization (ISO) and recommended for PQC migration by the BSI (German Federal Office for Information Security) and the ANSSI (French Cybersecurity Agency). It is closely related to the challenging time-computational problem inherent to algebraically unstructured lattices. However, hardware implementations of this scheme are required to verify its effectiveness in real-world applications. To the best of our knowledge, this is the first hardware implementation of FrodoKEM using High-Level Synthesis (HLS), which meets all requirements of the version submitted for standardization to ISO. The proposed design started with the profiling of the reference C software implementation using Valgrind software tools, to identify the functions that are the most time-consuming. The advantages of the proposed implementation include a 34% improvement in the speed metric of the Key Generation module in comparison with the reference software implementation. The results show that the key generation, encapsulation, and decapsulation use 26%, 39%, and 32%, respectively, of the total area utilization on the Artix-7.

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Author Biographies

Fernando Aparicio Urbano-Molano, Universidad del Valle

Fernando Urbano (SM’20) received the BSc degree in engineering physics from the Universidad del Cauca, Popayan, Colombia in 2005, the MSc degree in engineering (electronics), and the PhD in electrical and electronics engineering from the Universidad del Valle, Cali, Colombia in 2012 and 2025, respectively. He was a Visiting Research Scholar at Cryptographic Engineering Research Group (CERG) from George Mason University under the supervision of Dr. Kris Gaj from January to August 2024. From November 2006 to April 2020, he was an associate professor with the Department of Telematics at the college of electronics and telecommunication engineering at Universidad del Cauca, Colombia. His research interest are cryptographic engineering, digital systems design, reconfigurable hardware, embedded systems, Internet of Things, and Data Analysis

Jaime Velasco-Medina, Universidad del Valle

Jaime Velasco-Medina (SM’96) received the B.S. degree in electrical engineering from the Universidad del Valle, Cali, Colombia, in 1985, and the M.Sc. and Ph.D. degrees in microelectronics from the Institute National Polytechnic of Grenoble, Joseph Fourier University, Grenoble, France, in 1995 and 1999, respectively. In 1988, he joined the ATT Bell Laboratory, Allentown, PA, USA, as a Technical Staff Member for six months. He was the pioneer of the currentbased testing for analog and mixed signal circuits, and online testing of operational amplifiers. He is currently a Faculty Professor with the School of Electrical and Electronics Engineering, Universidad del Valle, and the Director of the Bionanoelectronics Research Group. He has authored or co-authored more than 50 IEEE papers and 50 peer-reviewed papers in other scientific events and journals. His current research interests include digital systems design for computer arithmetic and digital signal processing; test of analog and mixed-signal integrated circuits, hardware architectures for cryptography, quantum computing, wireless communications, citocomputation, and modeling of biological systems; the design of graphene-based digital circuits for spintronics; and computational design of bionanosensors and bionanomachines for drug delivery nanosystems. Dr. Velasco-Medina is a reviewer for the JETTA, IEEE-LATW, IEEE-SPL, IBERCHIP, IEEE-LASCAS, IEEE TRANSACTIONS ON VLSI SYSTEMS, IEEE TRANSACTIONS ON SIGNAL PROCESSING, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I, and many other international publications and conferences.

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Published

2025-08-30

How to Cite

Urbano-Molano, F. A., & Velasco-Medina, J. (2025). FrodoKEM Hardware Implementation for Post-Quantum Cryptography. IEEE Latin America Transactions, 23(10), 922–930. Retrieved from https://latamt.ieeer9.org/index.php/transactions/article/view/9651

Issue

Vol. 23 No. 10 (2025): Ordinary Issue

Section

Electronics