A Test IC for Wafer-Level Characterization of an IntraCMOS-MEMS Fabrication Process

Authors

  • Mónico Linares Aranda Instituto Nacional de Astrofísica, Óptica y Electrónica https://orcid.org/0000-0001-6206-0816
  • Luis Hernández Martínez Instituto Nacional de Astrofísica Óptica y Electrónica (INAOE) https://orcid.org/0000-0001-7178-7929
  • Javier De la Hidalga Wade Instituto Nacional de Astrofísica Óptica y Electrónica (INAOE)

Keywords:

Test devices, IC test, CMOS-MEMS, Integrated circuits, semiconductor devices

Abstract

Monitoring of fabrication processes and the measurement of the electrical and mechanical properties of materials and devices at the silicon-wafer level are of vital importance on integrated system technologies. In this work, a test integrated circuit (IC) for the development of an IntraCMOS-MEMS fabrication process is presented. The test devices contained in the test IC are designed in such a way that 1) they can be used in CMOS-MEMS fabrication technologies using different materials, 2) take into account the capabilities of the manufacturing infrastructure, and 3) consider the selected integrated fabrication scheme; thus, any monolithic CMOS-MEMS process can be evaluated before, during and after the fabrication. The acquired data from the test devices will be useful to identify possible electrical and/or mechanical variations, in the properties of the materials used and in the performance characteristics of the devices, due to the fabrication process. The information acquired will help to adjust the simulation routines and the analytical modeling expressions. Finally, using the infrastructure of the MEMS Innovation Laboratory (LIMEMS-INAOE México) preliminary experimental results are presented.

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Author Biographies

Mónico Linares Aranda, Instituto Nacional de Astrofísica, Óptica y Electrónica

Obtuvo los grados de Licenciatura, Maestría y Doctorado con especialidad Ciencias de la Electrónica en 1985, 1986 y 1996, respectivamente. Desde 1986 es investigador titular en el área de Electrónica del Instituto Nacional de Astrofísica, Óptica y Electrónica desde 1986. Ha publicado más de 100 artículos en conferencias y revistas científicas nacionales e internacionales en el campo de CIs y MEMS.

Luis Hernández Martínez, Instituto Nacional de Astrofísica Óptica y Electrónica (INAOE)

Obtuvo los grados de licenciado en Electrónica, Maestro en ciencias en Electrónica, y de Doctor en ciencias de la Electrónica en 1989, 1995 y 2001, respectivamente. Hizo un postdoctorado en la École Polytechnique Fédérale de Lausanne Laboratory of Nonlinear Systems en 2003. Actualmente es Investigador titular en el INAOE

Javier De la Hidalga Wade, Instituto Nacional de Astrofísica Óptica y Electrónica (INAOE)

Obtuvo los grados de Licenciado, Maestro y Doctor con especialidad Ciencias de la Electrónica en 1992, 1994 y 1998, respectivamente. Actualmente es investigador titular en el área de Electrónica del Instituto Nacional de Astrofísica, Óptica y Electrónica.

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Published

2021-08-25

How to Cite

Linares Aranda, M., Hernández Martínez, L. ., & De la Hidalga Wade, J. . (2021). A Test IC for Wafer-Level Characterization of an IntraCMOS-MEMS Fabrication Process. IEEE Latin America Transactions, 100(XXX). Retrieved from https://latamt.ieeer9.org/index.php/transactions/article/view/5165