Optimized implementation methodology for HIL FPGA simulations for power converters

Abstract

The growing complexity of power electronic systems demands simulation methods capable of high computational speed and accuracy. Traditional software‑based simulations exhibit long execution times and limited ability to reproduce critical operating conditions, while hardware experimentation may expose physical components to extreme scenarios that can compromise their integrity. This work presents an optimized methodology for modeling, discretizing, and implementing Boost, Buck, and Boost‑Buck converters on FPGA using LabVIEW. Mathematical models are derived from Kirchhoff’s laws and discretized through Euler’s method, followed by an algebraic conditioning stage that minimizes arithmetic operations and reduces clock‑cycle latency. Open‑loop tests comparing FPGA execution with PSIM simulations at 25% and 75% duty cycles demonstrate high fidelity in capacitor‑voltage and inductor‑current responses. Error growth at higher duty cycles is attributed to the UQ10.32 fixed‑point format. Overall, the proposed methodology offers an efficient and accurate alternative for real‑time‑oriented converter simulation, supporting safer and faster validation