Word-Line-Aware Garbage Collector for QLC-based NAND Flash Memories

Authors

Keywords:

NAND-Flash Memory, Garbage Collector, QLC Cells, Word-Line Awareness

Abstract

The Garbage Collector (GC) on NAND Flash memories is one of the most expensive operations in modern Solid-State Drives (SSD). However, it is essential to claim more free pages on SSDs. Various researches attempt to reduce the penalty of GC operations at different levels of the Input/Output (IO) path. Nevertheless, within the reviewed related works in Host-side, Open-Channel SSDs, and Device-side areas, we did not observe overlap with our research scope in how the logical pages are scattered in the NAND Word-Lines (WL) at the physical level, and how they impact performance degradation during the Garbage Collection operation. To reduce this bridge gap, we propose a new GC policy: Word-Line Aware Garbage Collector (WLA-GC). The WLA-GC focuses on reducing the Garbage Collector overhead by observing the physical distribution of valid logical pages within the WLs of a NAND Flash block to best select the victim blocks to be erased. Based on these criteria, the GC decisions are made by considering the latency the victim block will take to be fully erased. Analytical modeling shows that the proposed method outperforms the Vanilla GC in all cases, with an average performance of 25.4%. In comparison, the experimental results present a performance improvement of 55% in best-case scenarios.

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Author Biographies

Cassiano Silva de Campes, Universidade do Vale do Rio dos Sinos

Cassiano Silva de Campes received his BSc. in Computer Engineering at Universidade do Vale do Rio dos Sinos - UNISINOS, Brazil (2016); Sandwich PhD Student in Electrical and Computer Engineering at Sungkyunkwan University - SKKU, South Korea (2016-2019); PhD Student in Applied Computing at Universidade do Vale do Rio dos Sinos - UNISINOS, Brazil; Senior Embedded Software Engineer at Venko Networks, Porto Alegre, Brazil.

Rodrigo Marques de Figueiredo, Universidade do Vale do Rio dos Sinos

Rodrigo Marques de Figueiredo received his BSc. in Electrical Engineering at Universidade do Vale do Rio dos Sinos - UNISINOS (2005); MSc. in Applied Computing at Universidade do Vale do Rio dos Sinos - UNISINOS (2009); PhD in Geology at Universidade do Vale do Rio dos Sinos - UNISINOS (2016); Professor at UNISINOS University in Electrical Engineering undergraduate, and graduate programs.

Sandro José Rigo, Universidade do Vale do Rio dos Sinos

Sandro Jose Rigo is a Professor/Researcher in the Applied Computing Graduate Program Program – UNISINOS (since 2011); Head of the Undergraduate Course in Computer Science in UNISINOS (2011-2015); Head of the Graduate Degree Program in Applied Computer Science in UNISINOS (2015-2017); Dean of the UNISINOS Polytechnic School (2017). BSc in Computer Science at Pontifícia Universidade Católica do Rio Grande do Sul - PUCRS (1990); MSc in Computer Science at Universidade Federal do Rio Grande do Sul  - UFRGS (1993); Ph.D. in Computer Science at Universidade Federal do Rio Grande do Sul - UFRGS (2008). Professor and Researcher at UNISINOS University, since 1995. Scholarship for Productivity in Technological Development and Innovative Extension (DT-2) of the National Council for Scientific and Technological Development (CNPq). Innovation Consultant in knowledge transfer projects with the Industry. Main research areas: Artificial Intelligence, Semantic Web, Natural Language Processing, Robotic, Distance Education. Full papers published in journals: 31; Papers published in conference proceedings: 88; Books published and organized: 5; Book chapters published 10. Master Dissertations completed: 13; Co-oriented Master dissertations: 6; Master dissertations in progress: 9; Doctoral thesis in progress: 2; Software registered (INPI – Instituto Nacional de Propriedade Intelectual / National Institute of Intelectual Property): Since 2012: 6 software registered;

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Published

2026-04-09

How to Cite

Silva de Campes, C., Marques de Figueiredo, R., & José Rigo, S. (2026). Word-Line-Aware Garbage Collector for QLC-based NAND Flash Memories. IEEE Latin America Transactions, 24(5), 476–483. Retrieved from https://latamt.ieeer9.org/index.php/transactions/article/view/10214