A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words
Keywords:
Adaptability, Error Correction Codes, Fault Tolerance, Multiple Bit Errors, Single Bit Errors, ReliabilityAbstract
With the integration scale level reached in CMOS technology, memory systems provide a great storage capacity, but at the price of an augment in their fault rate. In this way, the probability of experiencing Single Cell Upsets or Multiple Cell Upsets have risen.
Error Correction Codes (ECC) are broadly employed to protect memory systems. Though, the inclusion of an ECC in a computer system adds, in each memory word, some extra bits used to detect and/or correct errors. In addition, encoding and decoding circuitries must be added, introducing overheads in area, delay, and power consumption.
Usually, when an ECC-based fault tolerance mechanism is designed, its fault tolerance properties cannot be modified. However, in some applications, current memory systems can suffer a variable fault rate during their operation. Thus, it seems very interesting that this mechanism would be able to adapt to these variable fault conditions.
This work proposes an Adaptive Fault-Tolerant mechanism based on ECC. This mechanism can adapt to different fault conditions, being able to correct and/or detect single and multiple bits in error. The Adaptive Fault-Tolerant mechanism proposed uses a unique encoder, that is, it is not necessary to re-encode the data to change the error coverage.
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