Complex Morphological Filtering For Serial, Parallel, GPU, SoC, PetaLinux And FPGA Execution


  • Tiago Bachiega de Almeida Universidade Federal de São Carlos
  • Emerson Carlos Pedrino Universidade Federal de São Carlos, Departamento de Computação, São Carlos, São Paulo, Brasil, CEP 13565-905
  • Márcio Merino Fernandes Universidade Federal de São Carlos, Departamento de Computação, São Carlos, São Paulo, Brasil, CEP 13565-905


Image processing, timing evaluation, morphological filtering, FPGA, embedded linux, many-core


Image processing is a vast field of research and extremely important for a large number of applications such as security systems, geoprocessing, medical technologies, etc. There are some applications that require a higher level of processing, requiring higher computing power. As an example of this requirement in image processing, morphological filtering with filter chains involving erosion and dilation may be used. This study aims to discuss the advantages and disadvantages between running these chains in a software context, using a personal computer and in a hardware context, using the ZedBoard board running these filters in baremetal, FPGA and embedded linux modes. In addition, a discussion on the possibilities of parallel hardware processing, inspired by the multi-core environment and its power, will be discussed.


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Author Biographies

Tiago Bachiega de Almeida, Universidade Federal de São Carlos

Graduando em Engenharia de Computação pela Universidade Federal de São Carlos, ingressante em 2015. Possui experiência nas áreas de desenvolvimento de software, visão computacional e processamento de imagens, desenvolvimento de sistemas embarcados com FPGA e inteligência artificial.

Emerson Carlos Pedrino, Universidade Federal de São Carlos, Departamento de Computação, São Carlos, São Paulo, Brasil, CEP 13565-905

Possui graduação em Engenharia Elétrica Eletrônica pela Universidade de São Paulo e Bacharelado em Física Computacional também pela Universidade de São Paulo- EESC (2016) e IFSC (2000) -, Mestrado em Engenharia Elétrica pela Universidade de São Paulo - EESC (2003) - e Doutorado em Engenharia Elétrica pela Universidade de São Paulo - EESC (2008). Também fez Pós doutorado em Engenharia Eletrônica (como Professor Visitante) no Departamento de Engenharia Eletrônica da Universidade de York, Inglaterra, colaborando no desenvolvimento de aplicações em hardware para o projeto: "Continuous on-line adaptation in many-core systems: from graceful degradation to graceful amelioration" com bolsa de pesquisa financiada pela FAPESP.

Márcio Merino Fernandes, Universidade Federal de São Carlos, Departamento de Computação, São Carlos, São Paulo, Brasil, CEP 13565-905

Possuo formação plena em Ciência da Computação: Universidade de São Paulo (graduação, 1989), Universidade Federal de São Carlos (mestrado, 1993) e The University of Edinburgh, UK (PhD, 1999). Atuou como membro do Comitê Gestor do INCT-SEC, o qual possibilitou diversas oportunidades de coordenação e atuação em atividades envolvendo setores acadêmicos e produtivos. Pró-Reitor de Administração da UFSCar.


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How to Cite

Bachiega de Almeida, T., Carlos Pedrino, E. ., & Merino Fernandes, M. (2021). Complex Morphological Filtering For Serial, Parallel, GPU, SoC, PetaLinux And FPGA Execution. IEEE Latin America Transactions, 18(10), 1675–1682. Retrieved from