Throughput Unfairness in Fair Arbitration Interconnection-Buses for Aerospace Embedded Systems


  • Salvador Ibarra Universidad Autonoma de Zacatecas
  • Remberto Sandoval-Arechiga
  • Maria Brox
  • Manuel Ortiz


Embedded System, aerospace


Modern embedded systems design based on the interconnection of Intelectual Property Cores (IP Cores) permit designers to focus on performance and functionality. Then, the selection of proper interconnection architecture is critical. A Network-on-Chip is an efficient and scalable solution for large systems. However, buses remain the best option to interconnect several IP Cores -up to eight-. The bus arbiter select which core transfer information, and its policy determines the system’s performance. A fair policy ensures that every core will get the same opportunities than the others. However, it lacks to offer a fair share of the bandwidth or transmission rate. Inspired by aerospace embedded systems such as CubeSats, in this work, we study the unfair transmission rate phenomenon in fair arbiters such as Round Robin, FIFO, and Lottery. Also, we propose a metric to compute the maximum number of IP Cores without bus saturation.


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