Hybrid sort algorithm implemented by High Level Synthesis
Keywords:
Sorting Algorithm, Zedboard, High Level Synthesis, Hardware AcceleratorAbstract
This paper proposes a hybrid data ordering algorithm which executes serial and parallel instructions. The implementation of the system is presented in a SoC (System on Chip) Zedboard of Xilinx. The design was done in high level language HLS (High Level Synthesis). It receives a vector of N elements and delivers the set of indexes of the L major elements ordered. The complexity of the algorithm is analyzed in a generic way. The required times and resources are evaluated and compared with well known algorithms.Downloads
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Published
2020-03-22
How to Cite
De Micco, L., Acosta, M., & Antonelli, M. (2020). Hybrid sort algorithm implemented by High Level Synthesis. IEEE Latin America Transactions, 18(2), 430–437. Retrieved from https://latamt.ieeer9.org/index.php/transactions/article/view/2918
Issue
Section
Special Isssue on Embedded Systems