FPGA Based Implementation of ImageZero Compression Algorithm

Abstract

The main goal of information compression is to achieve the greatest reduction possible of the volume of data. This action affects both storage and transmission. However, the most used algorithms have considerable latency and are not practical for real-world applications. In the image compression field, the situation is more complex because the resolutions are constantly increasing. Nowadays, it is common to deal with uncompressed images that exceed 60 MB. Dedicated compressors present strong restrictions of time, space and power so a thorough design and development should made.
In this work, an architecture of ImageZero compression lossless algorithm is presented. The algorithm was selected for its low latency both in encoding and decoding. The novelty of this work is the hardware implementation for this algorithm, based on FPGA. The synthesis results demonstrate that an increase in input image resolution does not affect the compression speedup. Also, the throughput for this proposal is greatest than other hardware implementations of image compressors.